DS1864K【PDF 6/72 页】KIT EVAL FOR DS1864

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SFP Laser Controller and

Diagnostic IC

NONVOLATILE MEMORY CHARACTERISTICS

(V CC = 2.97V to 5.5V, T A = -40°C to +95°C.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

EEPROM Writes

+70°C (Note 17)

50,000

Writes

Note 1:

Note 2:

Note 3:

Note 4:

Note 5:

Note 6:

Note 7:

Note 8:

Note 9:

Note 10:

Note 11:

Note 12:

Note 13:

Note 14:

Note 15:

Note 16:

Note 17:

All voltages are referenced to ground. Currents into the IC are positive, and currents out of the IC are negative.

Supply current is measured with all logic inputs at their inactive state (SDA = SCL = V CC ) and driven to well-defined logic

levels. All outputs are disconnected.

DAC0/DAC1 positions programmed to FFh and with outputs floating.

Full-scale is user programmable. The maximum voltage that the MON inputs read is approximately full-scale, even if the

voltage on the inputs is greater than full-scale.

This voltage defines the maximum range of the analog-to-digital (ADC) converter voltage, not the maximum V CC voltage.

Accuracy specification includes supply and temperature variations. Measured at 1.2V.

%FS refers to calibrated full scale in the case of internal calibration, and uncalibrated full scale in the case of external cali-

bration. Uncalibrated full scale is set at the factory and is specified in this data sheet as V CC FS (Factory), MON1 FS

(Factory), MON2 FS (Factory), and MON3 FS (Factory). Calibrated full scale is set by the user, allowing him to change any

of these scales for his instrumentation.

When used single-ended, MON1N must be connected to GND.

0.5%FS with 0.5dB (~11%) accuracy results in 16.4dB range. Assuming some overlap of the ranges, this scheme should

cover the required 26dB range.

See Figure 14 for thermometer error.

When the DACs are re-enabled, they ramp up to their final values. The ramp up starts from 0 and should not exceed its

final value at any point during its initial transient.

This spec is the time it takes, from RSSI voltage below the RSSI voltage trip threshold, to LOS asserted high.

Measured from the falling clock edge after the stop bit of the write transaction.

I 2 C interface timing shown for is for fast-mode (400kHz) operation. This device is also backward-compatible with I 2 C stan-

dard-mode timing.

C B ? total capacitance of one bus line in picofarads.

EEPROM write begins after a stop condition occurs.

This parameter is guaranteed by design.

6

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